1. Field of the Invention
The present invention relates to an image data transfer circuit and an image data transfer method for capturing image data sent from a video camera or the like into an LSI (Large Scaled Integrated Circuit), and more particularly, to exception control when an error occurs.
2. Description of the Related Art
FIG. 1 is a configuration diagram of a conventional moving image processing LSI.
This moving image processing LSI 1 performs image processing on image data sent thereto from a video camera 2, stores the processed image data in an external memory 3, and notifies an external host CPU (Central Processing Unit) 4 of the completion of the image processing, thereby enabling the host CPU 4 to read the image data after the image processing. This moving image processing LSI 1 comprises a camera interface (hereinafter, the interface is called the “I/F”) 10, an external memory I/F 20, image processing engine 30, and CPU I/F 40, all of which are interconnected through a common internal bus 50.
The camera I/F 10 transfers image data VDATA sent from the video camera 2 together with a vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC to the memory I/F 20 through the internal bus 50. The external memory I/F 20 writes the image data transferred from the camera I/F 10 into the external memory 3, as well as writes the image data into the external memory 3 in response to a request from the image processing engine 30, and reads the image data from the external memory 3 in response to a request from CPU I/F 40. The image processing engine 30 applies encoding processing and the like to the image data written into the external memory 3 by the camera I/F 10, and again stores the resulting image data in the external memory 3. The CPU I/F 40 reads the encoded image data from the external memory 3 and transfers the read image data to the host CPU 4.
The camera I/F 10 in the moving image processing LSI 1 comprises an input section 11, a filter 12, a FIFO (First-In First-Out) buffer 13, and an output section 14. The input section 11 inputs the image data VDATA sent from the video camera together with the vertical synchronizing signal VSYNC and horizontal synchronizing signal HSYNC, and outputs the image data signal VD together with an image data validity signal VA indicative of whether or not the image data signal VD is valid in units of pixels to the filter 12. Further, the input section 11 has an error detection function for detecting errors in the image data VDATA, and outputs a stop request signal STP to the filter 12 and output section 14 when an error is detected.
The input section 11, filter 12, FIFO buffer 13, and output section 14 are interconnected through pipe lines comprised of the image data signal VD and image data validity signal VA, such that the image data is written into the memory I/F 20 from the output section 14 through the internal bus 50.
In this camera I/F 10, the image data VDATA of the video camera 2 is input by the vertical synchronizing signal VSYNC and horizontal synchronizing signal HSYNC. The input section 11 captures the image data VDATA as valid data during a period in which the two synchronizing signals VSYNC, HSYNC are output. The input image data VDATA propagates the filter 12 and FIFO buffer 13 in order as the image data signal VD through pipeline processing together with the image data validity signal, and eventually is output from the output section 14 to the internal bus 50.
The filter 12, FIFO buffer 13, and output section 14 determine that new image data is input when the image data validity signal VA is output, and process the image data signal VD. The pipeline processing is performed in synchronism with the image data validity signal VA which is applied in units of pixels.
Upon detection of an error in the input image data VDATA, the input section 11 outputs the stop request signal STP to the filter 12 and output section 14 in order to stop the processing for capturing a frame including the image data. In this way, the pipeline processing under execution is stopped to stop processing the frame including the erroneous image data, alleviating a use load on the internal bus 50. Prior art documents related to image data transfer include the followings:
Japanese Patent Kokai No. 9-139828 (Patent Document 1); and
Japanese Patent Kokai No. 11-202848 (Patent Document 2).
However, the aforementioned camera I/F 10 has the following problems.
Specifically, as the stop request signal STP is output due to an error in input image data VDATA, the pipeline processing is stopped in the input section 11, filter 12, and output section 14. However, the transfer of image signal to the internal bus 50 in the output section can delay depending on a loading state on the internal bus 50. Therefore, when the stop request signal STP is output, image data of the previous normal frame may not have been transferred in some cases. In such a case, the data transfer is stopped by the stop request signal STP, leading to a problem that even the image data of the normal frame is broken.